In the manufacture of semiconductor integrated circuits, semiconductor chips are functionally tested at the wafer-level and then again after the chips are packaged. These tests are generally referred to as “wafer-level test” and “final test,” respectively. The wafer-level test confirms circuit functionality and final test confirms that the packaged chip works as intended.
Integrated circuit identification information, sometimes referred to as “chip identification” information, may include process lot number, wafer number and position on the wafer, and/or a chip serial number. This information can be used to determine causes of integrated circuit failures which occur during normal testing, such as during final test, as well as during field operation. Without chip identification information it is often difficult to relate a failure to specific integrated circuit parameters.
In the manufacture of memory chips, redundant circuitry is often built into memory arrays to achieve full functionality when the array has a limited number of defective rows or columns. However, redundant circuitry increases the complexity of a integrated circuit and consumes costly die area. An alternative approach to the memory yield problem uses a large memory array divided into a plurality of sub-memory regions or blocks, and only the fully functional sub-memory regions are identified for use. A chip identification circuit is coupled to an on-chip memory control unit to provide information on the functional memory size. For the redundant memory approach, a chip identification circuit disables the defective row and/or column and substitutes a redundant row and/or column. See, for example, Cenker et al., U.S. Pat. No. 4,228,528. Both approaches rely on a form of chip identification for proper operation of the memory chip.
Other uses for chip identification involves “trimming” (i.e., electrically adjusting or modifying) individual chips after wafer processing is complete in order to, for example, provide compensation to analog circuits for manufacturing variation. It may also be used to provide chip “personalization,” where certain functions of the chip are enabled or disabled after manufacture.
Conventional methods of encoding the foregoing types of chip identification information on an integrated circuit have been based on one-time programmable (OTP) read only memory (ROM) circuits formed in the chip. Programming mechanisms for OTP memory circuits include use of laser-blown fuses, electrically blown fuses and anti-fuses, and floating-gate technology. However, these techniques add significant cost to manufacturing the semiconductor integrated circuit. For example, floating-gate and anti-fuse ROM circuits may require additional wafer processing steps to form the structures to be programmed. And all of the techniques require additional circuitry that consumes costly silicon die area. Further, laser fusing requires precision alignment of the laser and the laser's energy must be tightly controlled to avoid damaging the chip being programmed.